AREA-power-delay-trade-off in logic synthesis.; by Michel R.C.M. Berkelaar
| Main Author: | BERKELAAR Michel R.C.M |
|---|---|
| Format: | Book |
| Terbitan: |
[tp]
|
| Subjects: | |
| Online Access: |
https://webpac.lib.itb.ac.id/search/detail/63450 |
Daftar Isi:
- xvii, 117 hlm.; gamb., tab.;25 cm