DESIGN & ANALYSIS OF A CHARGE RE-CYCLE BASED NOVEL LPHS ADIABATIC LOGIC CIRCUITS FOR LOW POWER APPLICATIONS
| Main Authors: | Sanjeev Rai, Govind Krishna Pal, Ram Awadh Mishra, Sudarshan Tiwari |
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| Format: | Article eJournal |
| Terbitan: |
, 2012
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| Subjects: | |
| Online Access: |
https://zenodo.org/record/2595934 |
Daftar Isi:
- This paper focuses on principles of adiabatic logic, its classification and comparison of various adiabatic logic designs. An attempt has been made in this paper to modify 2PASCL (Two Phase Adiabatic Static CMOS Logic) adiabatic logic circuit to minimize delay of the different 2PASCL circuit designs. This modifications in the circuits leads to improvement of Power Delay Product (PDP) which is one of the figure of merit to optimize the circuit with factors like power dissipation and delay of the circuit. This paper investigates the design approaches of low power adiabatic gates in terms of energy dissipation and uses of Simple PN diode instead of MOS diode which reduces the effect of Capacitances at high transition and power clock frequency. A computer simulation using SPECTRE from Cadence is carried out on different adiabatic circuits, such as Inverter, NAND, NOR, XOR and 2:1 MUX.