An Efficient Architecture of Vedic Multiplier using FinFet Based Pass Transistor Logic
| Main Authors: | B.Paulchamy, K.Kalpana, J.Jaya |
|---|---|
| Other Authors: | Blue Eyes Intelligence Engineering & Sciences Publication (BEIESP) |
| Format: | Article Journal |
| Bahasa: | eng |
| Terbitan: |
, 2020
|
| Subjects: | |
| Online Access: |
https://zenodo.org/record/5582455 |
| ctrlnum |
5582455 |
|---|---|
| fullrecord |
<?xml version="1.0"?>
<dc schemaLocation="http://www.openarchives.org/OAI/2.0/oai_dc/ http://www.openarchives.org/OAI/2.0/oai_dc.xsd"><contributor>Blue Eyes Intelligence Engineering & Sciences Publication (BEIESP)</contributor><creator>B.Paulchamy</creator><creator>K.Kalpana</creator><creator>J.Jaya</creator><date>2020-02-29</date><description>Multiplies is an important component in Digital Signal Processing (DSP) and communication systems. It is utilized in signal and image processing applications including convolution, Fast Fourier Transform (FFT) and correlation. Therefore, it is necessary to develop a multiplier with power efficient and speed to reduce the cost of the system. Vedic multiplier has been introduced to solve the problems of existing multiplier. It is based on 16 algorithms. These algorithms use algebra, arithmetic operations and geometry. Urdhva Tiryabhyam is widely employed formula which provides high speed and efficient. Vedic multiplies generates partial sums and products in single step. It has been designed using pass transistor logic which reduces the number of components utilized to build logic gates by removing unwanted transistors. This paper design a vedic multiplier with FinFET based pass transistor logic. The developed multiplies provides better performance and suitable for high speed applications. 2x2 and 4x4 vedic multipliers are developed and executed 180nm approach with Tanner EDA Tool 3.0.</description><identifier>https://zenodo.org/record/5582455</identifier><identifier>10.35940/ijeat.C5311.029320</identifier><identifier>oai:zenodo.org:5582455</identifier><language>eng</language><relation>issn:2249-8958</relation><rights>info:eu-repo/semantics/openAccess</rights><rights>https://creativecommons.org/licenses/by/4.0/legalcode</rights><source>International Journal of Engineering and Advanced Technology (IJEAT) 9(3) 2605-2611</source><subject>Vedic Multiplier, FinFET based Pass Transistor, High performance, Low power optimized circuit.</subject><subject>ISSN</subject><subject>Retrieval Number</subject><title>An Efficient Architecture of Vedic Multiplier using FinFet Based Pass Transistor Logic</title><type>Journal:Article</type><type>Journal:Article</type><recordID>5582455</recordID></dc>
|
| language |
eng |
| format |
Journal:Article Journal Journal:Journal |
| author |
B.Paulchamy K.Kalpana J.Jaya |
| author2 |
Blue Eyes Intelligence Engineering & Sciences Publication (BEIESP) |
| title |
An Efficient Architecture of Vedic Multiplier using FinFet Based Pass Transistor Logic |
| publishDate |
2020 |
| topic |
Vedic Multiplier FinFET based Pass Transistor High performance Low power optimized circuit ISSN Retrieval Number |
| url |
https://zenodo.org/record/5582455 |
| contents |
Multiplies is an important component in Digital Signal Processing (DSP) and communication systems. It is utilized in signal and image processing applications including convolution, Fast Fourier Transform (FFT) and correlation. Therefore, it is necessary to develop a multiplier with power efficient and speed to reduce the cost of the system. Vedic multiplier has been introduced to solve the problems of existing multiplier. It is based on 16 algorithms. These algorithms use algebra, arithmetic operations and geometry. Urdhva Tiryabhyam is widely employed formula which provides high speed and efficient. Vedic multiplies generates partial sums and products in single step. It has been designed using pass transistor logic which reduces the number of components utilized to build logic gates by removing unwanted transistors. This paper design a vedic multiplier with FinFET based pass transistor logic. The developed multiplies provides better performance and suitable for high speed applications. 2x2 and 4x4 vedic multipliers are developed and executed 180nm approach with Tanner EDA Tool 3.0. |
| id |
IOS16997.5582455 |
| institution |
ZAIN Publications |
| institution_id |
7213 |
| institution_type |
library:special library |
| library |
Cognizance Journal of Multidisciplinary Studies |
| library_id |
5267 |
| collection |
Cognizance Journal of Multidisciplinary Studies |
| repository_id |
16997 |
| subject_area |
Multidisciplinary |
| city |
Stockholm |
| province |
INTERNASIONAL |
| shared_to_ipusnas_str |
1 |
| repoId |
IOS16997 |
| first_indexed |
2022-06-06T04:58:24Z |
| last_indexed |
2022-06-06T04:58:24Z |
| recordtype |
dc |
| _version_ |
1734903842662776833 |
| score |
17.538404 |