An Enhanced FPGA Based Asynchronous Microprocessor Design Using VIVADO and ISIM
| Main Authors: | Rani, Archana; Manav Rachna International University, Grover, Naresh; Manav Rachna International University |
|---|---|
| Format: | Article info application/pdf eJournal |
| Bahasa: | eng |
| Terbitan: |
Institute of Advanced Engineering and Science
, 2018
|
| Subjects: | |
| Online Access: |
http://journal.portalgaruda.org/index.php/EEI/article/view/818 http://journal.portalgaruda.org/index.php/EEI/article/view/818/821 |
Daftar Isi:
- This paper deals with the novel design and implementation of asynchronous microprocessor by using HDL on Vivado tool wherein it has the capability of handling even I-Type, R-Type and Jump instructions with multiplier instruction packet. Moreover, it uses separate memory for instructions and data read-write that can be changed at any time. The complete design has been synthesized and simulated using Vivado. The complete design is targeted on Xilinx Virtex-7 FPGA. This paper more focuses on the use of Vivado Tool for advanced FPGA device. By using Vivado we get enhaced analysis result for better view of properly Route & Placed design.