On-chip Generation of Functional Tests with Reduced Delay and Power
| Main Authors: | Kumar Motamarri, Hemanth; University college of Engineering, JNTUK, Kumari, B. Leela; University college of Engineering, JNTUK |
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| Format: | Article info application/pdf eJournal |
| Bahasa: | eng |
| Terbitan: |
Institute of Advanced Engineering and Science
, 2017
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| Subjects: | |
| Online Access: |
http://journal.portalgaruda.org/index.php/EEI/article/view/570 http://journal.portalgaruda.org/index.php/EEI/article/view/570/892 |
Daftar Isi:
- This paper describes different methods on-chip test generation method for functional tests. The hardware was based on application of primary input sequences in order to allow the circuit to produce reachable states. Random primary input sequences were modeled to avoid repeated synchronization and thus yields varied sets of reachable states by implementing a decoder in between circuit and LFSR. The on-chip generation of functional tests require simple hardware and achieved high transition fault coverage for testable circuits. Further, power and delay can be reduced by using Bit Swapping LFSR (BS-LFSR). This technique yields less number of transitions for all pattern generation. Bit-swapping (BS) technique is less complex and more reliable to hardware miscommunications.