Reduction of Switches and DC Sources in Cascaded Multilevel Inverter
| Main Authors: | Devarajan, N.; Government College of Technology, Reena, A.; Government College of Technology |
|---|---|
| Format: | Article info application/force-download eJournal |
| Bahasa: | eng |
| Terbitan: |
Institute of Advanced Engineering and Science
, 2015
|
| Online Access: |
http://journal.portalgaruda.org/index.php/EEI/article/view/320 http://journal.portalgaruda.org/index.php/EEI/article/view/320/PDF |
Daftar Isi:
- Harmonics and increasing number of switches and DC sources for increasing level is the major issue in the cascaded multilevel inverter for the application of medium and high voltage power system applications. In this paper several new techniques are used to reduce the switches and DC sources, which overcome the disadvantages of cascaded multilevel inverter. The THD values for various levels (seven & nine) are compared with and without PWM technique.