Dataset for: Effective Logic Synthesis Flow for Threshold Logic Circuit Design
| Main Author: | Matos, Jody Maick |
|---|---|
| Other Authors: | Neutzling, Augusto, Mishchenko, Alan, Reis, Andre, Ribas, Renato |
| Format: | Dataset |
| Terbitan: |
Mendeley
, 2017
|
| Subjects: | |
| Online Access: |
https:/data.mendeley.com/datasets/ypvc8p99cb |
Internet
https:/data.mendeley.com/datasets/ypvc8p99cbLokasi
| Koleksi | Artikel mulono |
|---|---|
| Gedung | Teknologi Pangan UNISI |
| Institusi | Universitas Islam Indragiri |
| Kota | INDRAGIRI HILIR |
| Provinsi | RIAU |
| Kontak | Butuh informasi lebih lanjut? Hubungi pustakawan institusi ini. |