Step Width System Capture
| Main Author: | Bolaños, Yamir |
|---|---|
| Format: | Dataset |
| Terbitan: |
Mendeley
, 2020
|
| Subjects: | |
| Online Access: |
https:/data.mendeley.com/datasets/dgyhpm7h2k |
| ctrlnum |
0.17632-dgyhpm7h2k.2 |
|---|---|
| fullrecord |
<?xml version="1.0"?>
<dc><creator>Bolaños, Yamir</creator><title>Step Width System Capture </title><publisher>Mendeley</publisher><description> Hardware design for build a Step Width System Capture </description><subject>Electronic Design</subject><type>Other:Dataset</type><identifier>10.17632/dgyhpm7h2k.2</identifier><rights>CERN OHL version 1.2</rights><rights>http://www.ohwr.org/projects/cernohl/wiki</rights><relation>https:/data.mendeley.com/datasets/dgyhpm7h2k</relation><date>2020-04-01T20:42:14Z</date><recordID>0.17632-dgyhpm7h2k.2</recordID></dc>
|
| format |
Other:Dataset Other |
| author |
Bolaños, Yamir |
| title |
Step Width System Capture |
| publisher |
Mendeley |
| publishDate |
2020 |
| topic |
Electronic Design |
| url |
https:/data.mendeley.com/datasets/dgyhpm7h2k |
| contents |
Hardware design for build a Step Width System Capture |
| id |
IOS7969.0.17632-dgyhpm7h2k.2 |
| institution |
Universitas Islam Indragiri |
| affiliation |
onesearch.perpusnas.go.id |
| institution_id |
804 |
| institution_type |
library:university library |
| library |
Teknologi Pangan UNISI |
| library_id |
2816 |
| collection |
Artikel mulono |
| repository_id |
7969 |
| city |
INDRAGIRI HILIR |
| province |
RIAU |
| shared_to_ipusnas_str |
1 |
| repoId |
IOS7969 |
| first_indexed |
2020-04-08T08:18:27Z |
| last_indexed |
2020-04-08T08:18:27Z |
| recordtype |
dc |
| _version_ |
1686587539462291456 |
| score |
17.538404 |