Daftar Isi: SIGNATURE ANALYZER OF BUILT IN SELF TEST FOR ANALYZING STUCK AT FAULTS IN COMBINATIONAL LOGIC ICS

Main Authors:	Widianto, Widianto, Lis, Robert
Format:	Book PeerReviewed
Bahasa:	eng
Terbitan:	Fakultas Teknik Universitas Muhammadiyah Malang , 2019
Subjects:	TK Electrical engineering. Electronics Nuclear engineering
Online Access:	http://eprints.umm.ac.id/59719/18/Widianto%20Lis%20-%20signature%20analyzer%20built-in%20self%20test%20stuck-at-faults%20combinational%20logic%20ICs.pdf http://eprints.umm.ac.id/59719/19/Peer%20Review%20-%20Widianto%20-%20signature%20analyzer%20built-in%20self%20test%20stuck-at-faults%20combinational%20logic%20ICs.pdf http://eprints.umm.ac.id/59719/20/Similarity%20-%20Widianto%20Lis%20-%20signature%20analyzer%20built-in%20self%20test%20stuck-at-faults%20combinational%20logic%20ICs.pdf http://eprints.umm.ac.id/59719/ http://research-report.umm.ac.id/index.php/sentra/article/view/3012

Daftar Isi:

A signature analyzer of a built-in self test circuit is proposed to analyze stuck-at-faults occurring at input and output gates inside a combinational logic IC (Integrated Circuit). There are two types of the faults, namely stuck-at-1 and stuck-at-0. Logic values of the gate may be 1 and 0 values caused by stuck-at-1 and stuck-at-0, respectively. The test circuit consist of a pattern generator, multiplexers, demultiplexers, and the signature analyzer. In this paper, a feasibility of the test circuit is simulated using a Modelsim simulator. The IC of XXX0832 distributed by Nexperia.Co.Ltd is used as a CUT (Circuit Under Test). Simulation results show that the faults inside it may be analyzed to be detected