Hardware Design for Quadrature Phase Detection Algorithm in ECVT
| Main Authors: | Muttakin, Imamul; CTECH Labs Edwar Technology Co., Tangerang, Yusuf, Arbai; CTECH Labs Edwar Technology Co., Tangerang, ., Rohmadi; CTECH Labs Edwar Technology Co., Tangerang, Widada, Wahyu; CTECH Labs Edwar Technology Co., Tangerang, Taruno, Warsito P.; CTECH Labs Edwar Technology Co., Tangerang |
|---|---|
| Format: | Article info eJournal |
| Bahasa: | eng |
| Terbitan: |
IAES Indonesia Section
, 2014
|
| Subjects: | |
| Online Access: |
http://journal.portalgaruda.org/index.php/EECSI/article/view/408 http://journal.portalgaruda.org/index.php/EECSI/article/view/408/270 |
Daftar Isi:
- Core processing for calculating phase andamplitude of the detected signal was built on FPGA (Field-Programmable Gate-Array) platform. Phase shift demodulationalgorithm employs IP core provided by Xilinx FPGA. Directdigital synthesizer (DDS), multiplier, accumulator, and CORDIC(coordinate rotation digital computer) modules were used asexcitation-reference signal generator, signal multiplication,accumulation, and conversion to polar coordinate in order toconduct trigonometric operation respectively. Hardware designwas emulated on MATLAB-Xilinx System Generator to observeits performance. Phase detection range 0-114.58o and meanabsolute error 0.58o have been achieved. Data processing ratesolely at digital signal stage was approximately 100data/s suitablefor 32-channel ECVT (electrical capacitance volumetomography) system.