No RISC, no Fun: Comparison of Hardware Accelerated Hash Functions for XMSS
| Main Author: | Anonymous |
|---|---|
| Format: | Proceeding eJournal |
| Bahasa: | eng |
| Terbitan: |
, 2019
|
| Subjects: | |
| Online Access: |
https://zenodo.org/record/3556239 |
Daftar Isi:
- SHA-3.tar.gz : Bundle including a VexRiscv-CPU implementation (based on https://github.com/SpinalHDL/VexRiscv) with a hardware accelerator for SHA-3, and software implementation of XMSS (https://github.com/XMSS/xmss-reference) for the given RISC-V-CPU. SHA-256.tar.gz : Bundle including a VexRiscv-CPU implementation (based on https://github.com/SpinalHDL/VexRiscv) with a hardware accelerator for SHA-256, and software implementation of XMSS (https://github.com/XMSS/xmss-reference) for the given RISC-V-CPU.