On Vertical Integration Framework Element of Transistor-Transistor Logic
| Main Authors: | E.L. Pankratov, E.A. Bulaeva |
|---|---|
| Format: | Article eJournal |
| Terbitan: |
, 2019
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| Subjects: | |
| Online Access: |
https://zenodo.org/record/3530484 |
Daftar Isi:
- In this paper we introduce an approach to increase vertical integration of elements of transistor-transistor logic with function AND-NOT. Framework the approach we consider a heterostructure with special configuration. Several specific areas of the heterostructure should be doped by diffusion or ion implantation. Annealing of dopant and/or radiation defects should be optimized.