DESIGN OF A PROGRAMMABLE LOW POWER LOW DROP-OUT REGULATOR
| Main Author: | Jayanthi Vanama and G.L.Sampoorna |
|---|---|
| Format: | Article eJournal |
| Bahasa: | eng |
| Terbitan: |
, 2019
|
| Online Access: |
https://zenodo.org/record/3352152 |
Daftar Isi:
- A low power programmable low drop-out regulator capable of providing 1V output has been proposed. The regulator requires a supply voltage of 1.2V and works in the temperature range of -40 to 125 ̊C in nominal corner (i.e, normal doping for PMOS and NMOS Field Effect Transistors), yielding a load regulation of 3%. The output voltage level is controlled externally by means of 2 1-bit control signals. The circuit provides a DC gain of 30 dB and a maximum DC Power Supply Rejection Ratio of -35 dB and a worst case PSRR of -20 dB. Power dissipation in the load is nearly 100 μW.