Design and Implementation of a Low Powered Self-Testable ALU
| Main Authors: | Rakshan Ravindra Kulkarni, K. B. Ramesh |
|---|---|
| Format: | Article Journal |
| Terbitan: |
, 2022
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| Online Access: |
https://zenodo.org/record/6384174 |
Daftar Isi:
- Arithmetic logic unit (ALU) is an important part of the CPU as it performs all arithmetic and logic operations and calculations required by all processes running inside the CPU. Being such an important part within the processor it requires more power and therefore would be efficient and feasible if it could run at low power and test for faults in the circuit itself. This document focuses entirely on building a low-power ALU with the implementation of a built-in self-test (BIST) mechanism for efficient arithmetic and logical operations. The design uses energy-efficient circuits such as Wallace Tree Multipliers and Carry Look- Ahead Adders. The resulting design is synthesized and simulated using the field- programmable gate array (FPGA). The total power consumption of the design is 75mW, and the ALU has a self-test function.