Design and Analysis of Low Power High Speed Shift and Add Multiplier for Error Tolerant Applications
| Main Authors: | M. Manikanda Prabhu, K. B. Ramesh |
|---|---|
| Format: | Article Journal |
| Terbitan: |
, 2022
|
| Online Access: |
https://zenodo.org/record/6384106 |
Daftar Isi:
- In Adder circuit, the carry propagation from Least Significant Bit (LSB) to Most Significant Bit (MSB) is mostly responsible for the delay in the adder circuit. In modern VLSI technology errors of any kind are expected. Some errors like multimedia processing. In the circuit some glitches dissipate some dynamic power dissipation. If the glitches are removed or eliminated it improves the speed and power consumption of the circuit. For the current adder cell, the standard shift and add multiplier is an extension of error-tolerant mechanism. The objective of this paper is to design high speed adder to give an optimum result in terms of area, speed and power consumption. Various multipliers and adders are analysed and compare. Performance parameters are compared.