Daftar Isi: High Speed Gate Level Synchronous Full Adder Designs

Daftar Isi:

Digital computer systems are built on the foundation of addition. This paper presents three innovative gate level complete adder designs based on the elements of a conventional cell library: one using XNOR and multiplexer gates (XNM), another using XNOR, AND, Inverter, multiplexer, and complex gates (XNAIMC), and a third using XOR, AND, and complex gates (XAC). Many other existing gate level full adder realizations have been used to make comparisons. In view of broad simulations with a 32-bit carry-ripple adder execution focusing on three cycle, voltage, and temperature (PVT) corners of the great speed (low Vt) 65nm STMicroelectronics CMOS process, it was discovered that the XAC based full adder is found to be delay efficient compared to all of its gate level counterparts, even in comparison to all of their gate level counterparts. Using the complete adder cell from the library. The XNM-based full adder is determined to be area efficient, while the XNAIMC-based full adder provides a small speed and area tradeoff over the other two proposed adders.