Comparative Analysis of Efficient Designs of D Latch using 32nm CMOS Technology
| Main Authors: | Tanusha Beni Vyas, Shubhash Chandra |
|---|---|
| Format: | Article |
| Bahasa: | eng |
| Terbitan: |
, 2019
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| Subjects: | |
| Online Access: |
https://zenodo.org/record/3591483 |
Daftar Isi:
- In this paper we have proposed various efficient designs of low power D latch using 32nm CMOS technology. We have designed and simulated these circuits in HSpice simulation tool. In this simulation we have modified W L ratio of each transistor in each circuit. We have taken power supply of 0.9V. We have calculated average power consumed propagation delay and power delay product. Tanusha Beni Vyas | Shubhash Chandra "Comparative Analysis of Efficient Designs of D- Latch using 32nm CMOS Technology" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-3 | Issue-5 , August 2019, URL: https://www.ijtsrd.com/papers/ijtsrd26707.pdf