Vhdl Implementation of A Mips-32 Pipeline Processor
| Main Authors: | Kirat Pal Singh, Shivani Parmar |
|---|---|
| Format: | Article Journal |
| Terbitan: |
, 2012
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| Subjects: | |
| Online Access: |
https://zenodo.org/record/33247 |
Daftar Isi:
- This paper presents the design and implement a basic five stage pipelined MIPS-32 CPU. Particular attention will be paid to the reduction of clock cycles for lower instruction latency as well as taking advantage of high-speed components in an attempt to reach a clock speed of at least 100 MHz. The final results allowed the CPU to be run at over 200 MHz with a very reasonable chip area of around 900,000nm2.