Designed Implementation of Modified Area Efficient Enhanced Square Root Carry Select Adder
| Main Authors: | Priya Meshram, Mithilesh Mahendra, Parag Jawarkar |
|---|---|
| Format: | Article Journal |
| Terbitan: |
, 2015
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| Subjects: | |
| Online Access: |
https://zenodo.org/record/33092 |
Daftar Isi:
- In the design of Integrated Circuits, area occupancy plays a vital role because of increasing the necessity of portable systems. Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. In this paper, an area-efficient carry select adder by sharing the common Boolean logic term (CBL) with BEC is proposed. After logic simplification and sharing partial circuit, only one XOR gate and one inverter gate in each summation operation as well as one AND gate and one inverter gate in each carry-out operation are needed. Based on this modification a new modified 32-Bit Square-root CSLA (SQRT CSLA) architecture has been developed. The modified architecture has been developed using Common Boolean Logic(CBL). The proposed architecture has reduced area, power and delay.