Design of Low Power, Area-Efficient Carry Select Adder
| Main Authors: | Pallavi Saxena, Urvashi Purohit, Priyanka Joshi |
|---|---|
| Format: | Article Journal |
| Terbitan: |
, 2013
|
| Online Access: |
https://zenodo.org/record/32569 |
Daftar Isi:
- Design of low power and area-efficient logic systems forms an integral part and largest areas of research in the field of VLSI Design. Addition is the most fundamental arithmetic operation. In this paper, a low power, area-efficient carry select adder is proposed. CSA is one of the fastest adders used in dataprocessing systems to perform fast arithmetic operation. Secondly, structure of carry select adder is such that there is scope of reducing the area and power consumption. Thirdly, there is scope to reduce the area by using some add-one scheme. So, a Modified Carry Select Adder(MCSA) is designed by using single Ripple Carry Adder(RCA) and Binary to Excess-1 Converter (BEC) instead of dual RCAs in order to reduce the area and power consumption with small speed penalty. CSA and MCSA structures are designed for 8-bit, 16-bit, 32- bit and 64-bit. Result analysis shows that MCSA is better than CSA.