FPGA IMPLEMENTATION OF 16 BIT RISC CPU AND PERFORMANCE ANALYSIS
| Main Author: | DINESH B BORUDE |
|---|---|
| Format: | Article Journal |
| Bahasa: | eng |
| Terbitan: |
, 2017
|
| Subjects: | |
| Online Access: |
https://zenodo.org/record/1466625 |
Daftar Isi:
- RISC (Reduced Instruction Set Computer) found several application in the engineering. In this paper, authors have design, implement and performance analysis of a 16-bit Reduced Instruction Set (RISC) CPU using XILINX tool. The significant attribute of the RISC processor is that it is incredibly simple and sustains load/store architecture. The processor includes the ALU, Shifter, Register array, Instruction register, program counter, address register, Operand register, Comparator and Control unit. The performance parameters like area and propagation interruption are analyzed at 90 nm process tools using SPARTAN 3- XC3S400 FPGA and XILINX tool. https://journalnx.com/journal-article/20150137