DESIGN AND IMPLEMENTATION OF 8-BIT VEDIC MULTIPLIER
| Main Authors: | MISS. RUTUJA ABHANGRAO, MISS. SHILPA JADHAV, MISS PRIYANKA GHODKE, PROF. ALTAAF MULANI |
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| Format: | Article |
| Bahasa: | eng |
| Terbitan: |
, 2017
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| Subjects: | |
| Online Access: |
https://zenodo.org/record/1451178 |
Daftar Isi:
- Todays technology has raised demand for fast and real time signal processing operation. Multiplication is one of the most important arithmetic operations. In this paper, we have proposed design of vedic multiplier using Urdhva Tiryagbhyam sutra in Xilinx ISE. This design takes lesser time for operation than currently available multipliers .It encompasses wide era of image processing and digital signal processing in much efficient way with increase in speed and thus leading to higher performance rating. https://journalnx.com