A Novel Nano-Scaled SRAM Cell
| Main Authors: | Arash Azizi Mazreah, Mohammad Reza Sahebi, Mohammad T. Manzuri Shalmani |
|---|---|
| Format: | Article |
| Bahasa: | eng |
| Terbitan: |
, 2010
|
| Online Access: |
https://zenodo.org/record/1335330 |
Daftar Isi:
- To help overcome limits to the density of conventional SRAMs and leakage current of SRAM cell in nanoscaled CMOS technology, we have developed a four-transistor SRAM cell. The newly developed CMOS four-transistor SRAM cell uses one word-line and one bit-line during read/write operation. This cell retains its data with leakage current and positive feedback without refresh cycle. The new cell size is 19% smaller than a conventional six-transistor cell using same design rules. Also the leakage current of new cell is 60% smaller than a conventional sixtransistor SRAM cell. Simulation result in 65nm CMOS technology shows new cell has correct operation during read/write operation and idle mode.