High Speed and Ultra Low-voltage CMOS NAND and NOR Domino Gates
| Main Authors: | Yngvar Berg, Omid Mirmotahari |
|---|---|
| Format: | Article |
| Bahasa: | eng |
| Terbitan: |
, 2012
|
| Online Access: |
https://zenodo.org/record/1329190 |
Daftar Isi:
- In this paper we ultra low-voltage and high speed CMOS domino logic. For supply voltages below 500mV the delay for a ultra low-voltage NAND2 gate is aproximately 10% of a complementary CMOS inverter. Furthermore, the delay variations due to mismatch is much less than for conventional CMOS. Differential domino gates for AND/NAND and OR/NOR operation are presented.