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FPGA IMPLEMENTATION OF PATH TIMING METHOD FOR HARDWARE TROJAN DETECTION

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Main Author: O.Vignesh*1, H.Mangalam 2, T.Sugunabai3
Format: Article
Terbitan: , 2018
Subjects:
Digital Hardware Architecture
FPGA
GPP
Hardware Trojan
Side Channel Analysis
Online Access: https://zenodo.org/record/1230368
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Internet

https://zenodo.org/record/1230368

Lihat Juga

  • DESAIN HARDWARE TROJAN DAN TEKNIK PENDETEKSINYA MENGGUNAKAN SIDE CHANNEL ANALYSIS PADA HARDWARE KRIPTOGRAFI AES YANG DIIMPLEMENTASIKAN DALAM FPGA
    oleh: Bagus Hanindhito
    Terbitan: (2019)
  • A compressive sensing algorithm for hardware trojan detection
    oleh: M. Priyatharishini, et al.
    Terbitan: (2019)
  • Integrated Circuit AuthenticationHardware Trojans and Counterfeit Detection
    oleh: SpringerLink (Online service), et al.
  • FPGA Implementation of the "PYRAMIDS" Block Cipher
    oleh: A. AlKalbany, et al.
    Terbitan: (2007)
  • Hardware Trojan Detection and Mitigation in NoC using Key authentication and Obfuscation Techniques
    oleh: Thejaswini P, et al.
    Terbitan: (2022)
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