A Low-Area Fully-Reconfigurable Hardware Design of Fast Fourier Transform System for 3GPP-LTE Standard
| Main Authors: | Xin-Yu Shih, Yue-Qu Liu, Hong-Ru Chou |
|---|---|
| Format: | Article Journal |
| Bahasa: | eng |
| Terbitan: |
, 2017
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| Subjects: | |
| Online Access: |
https://zenodo.org/record/1130065 |
Daftar Isi:
- This paper presents a low-area and fully-reconfigurable Fast Fourier Transform (FFT) hardware design for 3GPP-LTE communication standard. It can fully support 32 different FFT sizes, up to 2048 FFT points. Besides, a special processing element is developed for making reconfigurable computing characteristics possible, while first-in first-out (FIFO) scheduling scheme design technique is proposed for hardware-friendly FIFO resource arranging. In a synthesis chip realization via TSMC 40 nm CMOS technology, the hardware circuit only occupies core area of 0.2325 mm2 and dissipates 233.5 mW at maximal operating frequency of 250 MHz.