FPGA Implementation of the "PYRAMIDS" Block Cipher
| Main Authors: | A. AlKalbany, H. Al hassan, M. Saeb |
|---|---|
| Format: | Article |
| Bahasa: | eng |
| Terbitan: |
, 2007
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| Subjects: | |
| Online Access: |
https://zenodo.org/record/1081753 |
Daftar Isi:
- The “PYRAMIDS" Block Cipher is a symmetric encryption algorithm of a 64, 128, 256-bit length, that accepts a variable key length of 128, 192, 256 bits. The algorithm is an iterated cipher consisting of repeated applications of a simple round transformation with different operations and different sequence in each round. The algorithm was previously software implemented in Cμ code. In this paper, a hardware implementation of the algorithm, using Field Programmable Gate Arrays (FPGA), is presented. In this work, we discuss the algorithm, the implemented micro-architecture, and the simulation and implementation results. Moreover, we present a detailed comparison with other implemented standard algorithms. In addition, we include the floor plan as well as the circuit diagrams of the various micro-architecture modules.