Fabrication and Characterization of Poly-Si Vertical Nanowire Thin Film Transistor
| Main Authors: | N. Shen, T. T. Le, H. Y. Yu, Z. X. Chen, K. T. Win, N. Singh, G. Q. Lo, D. -L. Kwong |
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| Format: | Article Journal |
| Bahasa: | eng |
| Terbitan: |
, 2011
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| Subjects: | |
| Online Access: |
https://zenodo.org/record/1059559 |
Daftar Isi:
- In this paper, we present a vertical nanowire thin film transistor with gate-all-around architecture, fabricated using CMOS compatible processes. A novel method of fabricating polysilicon vertical nanowires of diameter as small as 30 nm using wet-etch is presented. Both n-type and p-type vertical poly-silicon nanowire transistors exhibit superior electrical characteristics as compared to planar devices. On a poly-crystalline nanowire of 30 nm diameter, high Ion/Ioff ratio of 106, low drain-induced barrier lowering (DIBL) of 50 mV/V, and low sub-threshold slope SS~100mV/dec are demonstrated for a device with channel length of 100 nm.