Implementation of Optimized 64x64-bit Vedic Multiplier
| Main Authors: | Mohammad Nasiruddin, Prashant S Sharma, Vijay S Chourasia |
|---|---|
| Format: | Article eJournal |
| Bahasa: | eng |
| Terbitan: |
, 2019
|
| Subjects: | |
| Online Access: |
https://zenodo.org/record/3582202 |
Daftar Isi:
- The need of high speed multiplier is increasing day by day because of high speed computer applications. The multiplication process consumes significantly more time for calculation. This computation time must be reducing in order to increase the speed of the system. In this paper, we have proposed a high speed 64x64-bit Vedic Multiplier by making use of Urdhava Tiryakbhyam Sutra of Vedic mathematics. Urdhva-Tiryagbhyam is the most efficient algorithm which provides high speed multiplication of numbers of any size. Multiplier is one of the important hardware block in most Digital Signal Processing (DSP) systems. Design of multiply and accumulate unit (MAC) unit which consists of multiplier unit, adder and accumulator will be implemented. Design synthesis and simulation of 64-bit Vedic multiplier performed by using Xilinx Spartan 6 Starter Kit. Combinational path delay obtained for 64-bit Vedic multiplier is 7.040nanosecond with frequency of 142.052MHz. Further the proposed design is compared with the existing 64-bit multiplier in terms of delay.