Indonesia OneSearch
Gravitasi
  • Cari
  • On-Chip Generation of Function...
  • Lokasi
Cover Image

On-Chip Generation of Functional Tests with Reduced Delay and Power

Tersimpan di:
Main Authors: Hemanth Kumar Motamarri, B Leela Kumari
Format: Article
Terbitan: , 2017
Subjects:
Built-in test generation
functional tests
reachable states
Bit Swapping LFSR (BS-LFSR)
Online Access: https://zenodo.org/record/4107749
  • Lokasi
  • Deskripsi
  • Daftar Isi
  • Preview
  • Tampilan Petugas

Internet

https://zenodo.org/record/4107749

Lihat Juga

  • On-chip Generation of Functional Tests with Reduced Delay and Power
    oleh: Kumar Motamarri, Hemanth; University college of Engineering, JNTUK, et al.
    Terbitan: (2017)
  • A Simulation Experiment on a Built-In Self Test Equipped with Pseudorandom Test Pattern Generator and Multi-Input Shift Register (MISR)
    oleh: Afaq Ahmad
    Terbitan: (2010)
  • FPGA-based Design System for a Two-Segment Fibonacci LFSR Random Number Generator
    oleh: Zulfikar, et al.
    Terbitan: (2017)
  • An approach to Measure Transition Density of Binary Sequences for X-filling based Test Pattern Generator in Scan based Design
    oleh: Sabir Hussain, et al.
    Terbitan: (2018)
  • Tinjauan pada Algoritma LFSR (Linear Feedback Shift Register) dalam Reposisi XOR dalam Pencarian Bilangan Acak Terbaik: Studi Kasus LFSR dengan 4 Bit dan 6 Bit
    oleh: Sulistiyanto, Angga
    Terbitan: (2018)
© 2025 Perpustakaan Nasional Republik Indonesia
Loading...