Reduction of Leakage Power in Digital Logic Circuits Using Stacking Technique in 45 Nanometer Regime
| Main Authors: | P.K. Sharma, B. Bhargava, S. Akashe |
|---|---|
| Format: | Article |
| Bahasa: | eng |
| Terbitan: |
, 2013
|
| Online Access: |
https://zenodo.org/record/1335856 |