Vedic Mathematics Based 32-Bit Multiplier Design for High Speed Low Power Processors
| Main Authors: | Saha, P., Banerjee, A., Dandapat, A., Bhattacharyya, P. |
|---|---|
| Format: | Article Journal |
| Terbitan: |
, 2011
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| Subjects: | |
| Online Access: |
https://zenodo.org/record/1148082 |
Internet
https://zenodo.org/record/1148082Lokasi
| Koleksi | Cognizance Journal of Multidisciplinary Studies |
|---|---|
| Gedung | Cognizance Journal of Multidisciplinary Studies |
| Institusi | ZAIN Publications |
| Kota | Stockholm |
| Provinsi | INTERNASIONAL |
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